Chris Kluka: Network driver development

Project Plan



Milestones and Timeline

Given that drivers for this card exist for BSD and Linux, implementing a driver for gPXE should not be too difficult. After looking through the gPXE API and some of the other drivers in gpxe/src/drivers/net/, I feel confident that I would be able to implement the 5 core functions of the gPXE API.

I speculate that almost (if not) all code will be written in C. The possibility exists to compose a few snippets in ASM to support one of last year's SOC project which was based around code optimization. However, at this point, I have not been able to identify any specific areas of the driver which would benefit significantly from assembler optimization.

Then, once the driver is implemented, (time pending) I would write a basic testing class and polish some documentation around the driver. As driver implementation is relatively straight forward, I do not expect more than 3-4 pages of documentation for this task.


May 4-20: Read through the gPXE code base, familiarize self with project and project's expectations

May 23: begin creating class diagrams of existing drivers. This is to include the Linux, the BSD, and (if possible), some other OS's drivers Begin designing driver outline.

May 23: Compose emails to the authors of the previous drivers requesting any documentation on hardware specifics. I was unable to find a datasheet on this device, but was able to find a datasheet on what I believe is its IC ( I will have to verify that this is the correct datasheet.

May 25: Completed class diagram of at least one of the above OS's.

May 30: Completed class diagram of at least two of the above. Specific attention to hardware API is the most important part.

June 4: Hopefully by this point I have collected sufficient information to compose a definitive hardware API for this device.

June 4: Compose a list of functions available on the card as well as DMA call documentation. Basically, have a completed summary of how the card wants to be 'talked to'.

June 5-9: Compose a class diagram of the whole driver. This will largely be tinplating off of the existing gPXE drivers for other NIC's and the other OS's drivers for this NIC.

June 10-20: Write the driver.

June 21: Cross fingers and hopefully it's pretty much done.

June 22-30: TBA; hopefully moving on to documentation/testing, but available for rewriting the driver/bug stomping/etc…

July 1-5: Collaboration with mentor as to progress up until this point, speculation on the other half of the time. Basically, reassess my position/timeline.

July 6: midterm review

July 7-15: If not done, documentation/testing.

July 15-august 10: At this point, if I'm done, I'd like to start work on a 2nd driver which hopefully can be completed in 1/2 to 1/3 of the time of the first driver. If I'm not done, reassess my position and timeline and schedule accordingly.

August 10-17, more testing, more documentation. Hopefully end up with (a) completed driver(s) with testing units and complete documentation including a hardware API for this device.


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