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====== Stefan Hajnoczi: GDB Remote Debugging ====== ===== Journal ===== ==== Week 1 ==== **Milestone:** Set up IDT and write an interrupt handler. === Fri May 23 === Some notes after chatting with mdc and mcb30: * Place IDT code in ''arch/i386/transitions/librm.S'' - in similar places to ''lgdt'' and ''sgdt''. * GDB stub should be written with portability in mind, separate out arch-specific parts. * GDB stub should be a build option. * Source-level debugging and symbols should work (mostly) out-of-the-box due to ELF build. === Sat May 24 === Git commit: [[http://git.etherboot.org/?p=people/stefanha/gpxe.git;a=commit;h=ac29ad53aff6e89f12bd5a163861d1afb1846049|ac29ad53aff6e89f12bd5a163861d1afb1846049]] Implemented an interrupt handler in ''arch/i386/transitions/librm.S''. It currently sets ''eax'' to ''0xcafebabe'' and spins in an infinite loop. Have tested that it is working using QEMU. === Sun May 25 === Git commits: [[http://git.etherboot.org/?p=people/stefanha/gpxe.git;a=commit;h=12144ffbfadef9c6597f9ac754685223bb736368|12144ffbfadef9c6597f9ac754685223bb736368]] and [[http://git.etherboot.org/?p=people/stefanha/gpxe.git;a=commit;h=1ff72edaa0c68966e1bc102ae5167d714eeb03e6|1ff72edaa0c68966e1bc102ae5167d714eeb03e6]] When GDB reads or writes registers on x86, it wants a snapshot like this: ''EAX'', ''ECX'', ''EDX'', ''EBX'', ''ESP'', ''EBP'', ''ESI'', ''EDI'', ''EIP'', ''EFLAGS'', ''CS'', ''SS'', ''DS'', ''ES'', ''FS'', ''GS''. This snapshot is a blob that gets sent between the GDB stub and GDB. The interrupt handler now takes this register snapshot and passes it to the GDB stub. It also applies the register snapshot to the actual CPU state when the GDB stub returns. So if the GDB stub changes ''EAX'' in the register snapshot, then the ''EAX'' register will be changed when the interrupt handler returns. Still need to: * Check with mcb30 whether the IDT setup code is sane. * Distinguish between incoming interrupt numbers and convert to POSIX signo. * Reduce the number of IDT entries to the minimum (16 should be fine). * Support interrupts that push error code onto the stack.
