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<tt>I wrote:</tt>
<blockquote type="cite" cite="mid:4B12E7C8.9060309@YRDSB.Edu.On.Ca"><tt>
Bernhard Kohl wrote:
</tt>
<blockquote type="cite" cite="mid:4B06ABED.8020108@nsn.com">
<title>[Etherboot-developers] [PATCH] [pciextra] Restore the PCI
COMMAND register after writing to the BARs</title>
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<p><tt><font size="2">Hi,<br>
<br>
This seems to be necessary for some types of PCI devices. We got
problems<br>
when using gPXE in KVM virtual machines with direct PCI device access.<br>
<br>
The PCI spec says:<br>
Decode (I/O or memory) of a register is disabled via the command<br>
register before<br>
sizing a Base Address register. Software saves the original value of the<br>
Base<br>
Address register, writes 0FFFFFFFFh to the register, then reads it back.<br>
...<br>
The original value in the Base Address register is restored before<br>
reenabling<br>
decode in the command register of the device.</font></tt></p>
</blockquote>
<tt>Thanks, Bernhard. This has been noted at
<a href="http://support.etherboot.org/index.php?do=details&task_id=40" class="moz-txt-link-freetext" moz-do-not-send="true">http://support.etherboot.org/index.php?do=details&task_id=40</a></tt></blockquote>
<tt><br>
Bernhard, I notice that we might actually wish to disable memory space
access... I've made a modified patch, attached. Could you please test
it out? Also available at:
<a href="http://git.etherboot.org/?p=people/sha0/gpxe.git;a=commitdiff;h=86761eafd7451b084ca67c3b10852e50a85f9ee1" class="moz-txt-link-freetext">http://git.etherboot.org/?p=people/sha0/gpxe.git;a=commitdiff;h=86761eafd7451b084ca67c3b10852e50a85f9ee1</a><br>
<br>
Thanks again!<br>
<br>
- Shao Miller<br>
</tt>
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